A NAND-type flash memory is one of a nonvolatile semiconductor memory device that can record much more information in a small chip, according to a multi-level technology which enables one memory cell transistor of a plurality of NAND strings forming a memory cell array to store the information for two bits or three bits. Together with a widespread use of the NAND-type flash memories for mobile devices handling large capacity data such as image and moving image, their demand is rapidly increasing.
A NAND-type flash memory is provided with a sense amplifier circuit and a data latch circuit in each bit line of a memory cell array, so that a writing operation and a reading operation can be simultaneously performed on a page basis. Here, the sense amplifier circuit is a circuit for controlling the reading operation and the writing operation. The data latch circuit is a circuit for temporarily storing the data read by the sense amplifier circuit from the memory cell, to output the above data externally and temporarily storing the written data input externally, to pass the above data to the sense amplifier.
One page is basically defined as about 2 KB. After reading out the data of about 2 KB, simultaneously the data is externally output in serial, thereby raising the data throughput. By changing the capacity of one writing and reading data from 2 KB to 4 KB in a page basis operation, the writing and reading throughput can be enhanced. At the present, with a page basis of 8 KB, the 16 KB data, double the page, can be simultaneously written and read out.
In a NAND-type flash memory, scale down of a memory cell array is developing, and in order to reduce a chip size, a reduction in the peripheral circuit size also becomes very important. Of the peripheral circuit, as it requires the same number of the sense amplifier circuits and the data latch circuits as the number of pages, the number of the both circuits is huge, occupying 10% of the chip size. In order to reduce the chip size, we have to challenge the size reduction of the sense amplifier circuit and the data latch circuit as well as the miniaturization of a memory cell array.
In this embodiment, a size reduction of the data latch circuit is considered. In this respect, there is posed a challenge to reduce the number of transistors and the size of a transistor itself. When the data latch circuit is scaled down, however, the circuit itself becomes fragile, deteriorating the data keeping ability and an erroneous inversion of the stored data may happen in some cases. Further, currents consumed for data transfer between the data latch circuits and the sense amplifier circuits become a considerable problem from a viewpoint of reducing the current consumption.